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ks57c5204/c5208/p5208/c5304/c5308/p5308/c5312/p5312 product overview 1- 1 1 product overview overview the ks57c5204/c5208/c5304/c5308/c5312 single-chip cmos microcontroller has been designed for high- performance using sam 47 (samsung arrangeable microcontrollers). sam 47, samsung's newest 4-bit cpu core is notable for its low energy consumption and low operating voltage. you can select from three rom sizes: 4k, 8k, or 12k bytes. except for the difference in rom size, the features and functions of the ks57c5204 and the ks57c5208 are identical and the ks57c5304, ks57c5308, and the ks57c5312 are identical. with it's dtmf generator, watchdog timer function, and versatile 8-bit timer/counters, the ks57c5204/c5208 /c5304/c5308/c5312 offers an excellent design solution for a wide variety of telecommunication applications. up to 35 pins of the available 42-pin sdip or 44-pin qfp package for the ks57c5204/c5208, and up to 23 pins of the available 30-pin sdip or 32-pin sop package for the ks57c5304/c5308/c5312 can be assign to i/o. six vectored interrupts for ks57c5204/c5208 and four vectored interrupts for ks57c5304/c5308/c5312 provide fast response to internal and external events. in addition, the ks57c5204/c5208/c5304/c5308/c5312's advanced cmos technology provides for low power consumption and a wide operating voltage range. otp the ks57c5204/c5208 microcontroller is also available in otp (one time programmable) version, ks57p5208. the ks57c5304/c5308/c5312 microcontroller is also available in otp (one time programmable) version, ks57p5308/p5312. the ks57p5208/p5308/p5312 microcontroller has an on-chip 8k-byte (p5208/p5308) or 12k-byte (p5312) one-time- programable eprom instead of masked rom. the ks57p5208 is comparable to ks57c5204/c5208, both in function and in pin configuration. also, the ks57p5308/p5312 is comparable to the ks57c5304/c5308/c5312, both in function and in pin configuration.
product overview k s57c5204/c5208/p5208/c5304/c5308/p5308/c5312/p5312 1- 2 features memory 768 4-bit ram 4,096 8-bit rom (ks57c5204/c5304) 8,192 8-bit rom (ks57c5208/c5308) 12,288 8-bit rom (ks57c5312) i/o pins input only: 4 pins (ks57c5204/c5208) 1 pins (ks57c5304/c5308/c5312) i/o: 35 pins (ks57c5204/c5208) 23 pins (ks57c5304/c5308/c5312) n-channel open-drain i/o: 8 pins memory-mapped i/o structure data memory bank 15 dtmf generator 16 dual-tone frequencies for tone dialing 8-bit basic timer programmable interval timer watchdog timer two 8-bit timer/counters programmable 8-bit timer external event counter function arbitrary clock frequency output watch timer real-time and time interval generation four frequency outputs to the buz pin bit sequential carrier supports 16-bit serial data transfer in arbitrary format interrupts 3 external interrupt vectors (ks57c5204/c5208) 1 external interrupt vectors (ks57c5304/c5308/c5312) 3 internal interrupt vectors 2 quasi-interrupts power-down modes idle: only cpu clock stops stop: system clock stops oscillation sources crystal, or ceramic for main system clock main system clock frequency: 0.4?6.0 mhz (typical) cpu clock divider circuit (by 4, 8, or 64) instruction execution times 0.95, 1.91, and 15.3 m s at 4.19 mhz 1.12, 2.23, 17.88 m s at 3.58 mhz 0.67, 1.33, 10.7 m s at 6.0 mhz operating temperature ? 40 c to 85 c operating voltage range 1.8 v to 5.5 v package types 42 sdip, 44 qfp (ks5 7c5204/c5208) 30 sdip, 32 sop (ks57c5304/c5308/c5312)
ks57c5204/c5208/p5208/c5304/c5308/p5308/c5312/p5312 product overview 1- 3 block diagram program status word flags arithmetic and logic unit instruction decoder internal interrupts reset interrupt control block stack pointer clock program memory ks57c5204/c5304: 4kbytes ks57c5208/c5308: 8kbytes ks57c5312: 12kbytes 768x4-bit data memory input port 1 p1.0/int0 p1.1/int1 p1.2/int2 p1.3/int4 p9.0 - p9.2 x out x in program counter 8-bit timer/ counter 0 watchdog timer note: ks57c5304/c5308/c5312 does not use p1.1/int1, p1.2/int2, p1.3/int4, p3.2, p3.3, int1, int2, int4, p8.0-p8.3, and p9.0-p9.2. 8-bit timer/ counter 1 i/o port 3 i/o port 2 i/o port 7 i/o port 6 i/o port 9 i/o port 8 basic timer watch timer i/o port 5 i/o port 4 dtmf generator p2.0/tclo0 p2.1/tclo1 p2.2/clo p2.3/buz p3.0/tcl0 p3.1/tcl1 p3.2 p3.3 p4.0/btco p4.1-4.3 p5.0-p5.3 dtmf p6.0-p6.3/ ks0-ks3 p7.0-p7.3/ ks4-ks7 p8.0 - p8.3 int0, int1, int2, int4 figure 1-1. ks57c5204/c5208/c5304/c5308/c5312 simplified block diagram
product overview k s57c5204/c5208/p5208/c5304/c5308/p5308/c5312/p5312 1- 4 pin assignments p1.0/int0 p1.1/int1 p1.2/int2 p1.3/int4 p2.0/tclo0 p2.1/tclo1 p2.2/clo p2.3/buz p3.0/tcl0 p3.1/tcl1 v dd v ss x out x in test p4.0/btco p4.1 reset p3.2 p3.3 p4.2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 p9.2 p9.1 p9.0 dtmf p7.3/ks7 p7.2/ks6 p7.1/ks5 p7.0/ks4 p6.3/ks3 p6.2/ks2 p6.1/ks1 p6.0/ks0 p5.3 p5.2 p5.1 p5.0 p8.3 p8.2 p8.1 p8.0 p4.3 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 ks57c5204/c5208 (42-sdip-600) figure 1-2. ks57c5204/c5208 pin assignment diagram (42-sdip)
ks57c5204/c5208/p5208/c5304/c5308/p5308/c5312/p5312 product overview 1- 5 dtmf p9.0 p9.1 p9.2 nc p1.0/int0 p1.1/int1 p1.2/int2 p1.3/int4 p2.0/tclo0 p2.1/tclo1 ks57c5204 /c5208 (44-qfp-1010b) 1 2 3 4 5 6 7 8 9 10 11 p7.3/ks7 p7.2/ks6 p7.1/ks5 p7.0/ks4 p6.3/ks3 p6.2/ks2 p6.1/ks1 p6.0/ks0 p5.3 p5.2 p5.1 p5.0 p8.3 p8.2 p8.1 p8.0 p4.3 nc p4.2 p3.3 p3.2 reset 34 35 36 37 38 39 40 41 42 43 44 p2.2/clo p2.3/buz p3.0/tcl0 p3.1/tcl1 v dd v ss x out x in test p4.0/btco p4.1 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 figure 1-3. ks57c5204/c5208 pin assignment diagram (44-qfp)
product overview k s57c5204/c5208/p5208/c5304/c5308/p5308/c5312/p5312 1- 6 v ss x out x in test p4.0/btco p4.1 reset p4.2 p4.3 p5.0 p5.1 p5.2 p5.3 p6.0/ks0 p6.1/ks1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 v dd p3.1/tcl1 p3.0/tcl0 p2.3/buz p2.2/clo p2.1/tclo1 p2.0/tclo0 p1.0/int0 dtmf p7.3/ks7 p7.2/ks6 p7.1/ks5 p7.0/ks4 p6.3/ks3 p6.2/ks2 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ks57c5304/c5308/c5312 (30-sdip-400) figure 1-4. ks57c5304/c5308/c5312 pin assignment diagram (30-sdip) v ss x out x in test p4.0/btco p4.1 reset p4.2 nc p4.3 p5.0 p5.1 p5.2 p5.3 p6.0/ks0 p6.1/ks1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v dd p3.1/tcl1 p3.0/tcl0 p2.3/buz p2.2/clo p2.1/tclo1 p2.0/tclo0 p1.0/int0 nc dtmf p7.3/ks7 p7.2/ks6 p7.1/ks5 p7.0/ks4 p6.3/ks3 p6.2/ks2 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 ks57c5304/c5308/c5312 (32-sop-450a) figure 1-5. ks57c5304/c5308/c5312 pin assignment diagram (32-sop)
ks57c5204/c5208/p5208/c5304/c5308/p5308/c5312/p5312 product overview 1- 7 pin descriptions table 1-1. ks57c5204/c5208 pin descriptions pin name pin type reset value description pin number share pin circuit type p1.0 p1.1 p1.2 p1.3 i i 4-bit input port. 1-bit and 4-bit read and test is possible. each pull-up resistors are assignable by software. 1 (39) 2 (40) 3 (41) 4 (42) int0 int1 int2 int4 a-4 p2.0 p2.1 p2.2 p2.3 i/o i 4-bit i/o port. 1-bit and 4-bit read/write and test is possible. individual pins are software configurable as input or output. 5 (43) 6 (44) 7 (1) 8 (2) tclo0 tclo1 clo buz d-2 p3.0 p3.1 p3.2 p3.3 4-bit pull-up resistors are software assignable to input pins and are automatically disabled for output pins. ports 2 and 3 can be paired to enable 8-bit data transfer. 9 (3) 10 (4) 19 (13) 20 (14) tcl0 tcl1 d-4 p4.0 p4.1 p4.2 p4.3 p5.0-p5.3 i/o i 4-bit i/o ports. 1-bit and 4-bit read/write and test is possible. individual pins are software configurable as input or output. 4-bit pull-up resistors are software assignable to input pins and are automatically disabled for output pins. n-channel open-drain or push-pull output can be selected by software (1-bit unit) ports 4 and 5 can be paired to support 8-bit data transfer. 16 (10) 17 (11) 21 (15) 22 (17) 27-30 (22-25) btco e-2 p6.0-p6.3 p7.0-p7.3 i/o i 4-bit i/o ports. 1-bit or 4-bit read/write and test is possible. individual pins are software configurable as input or output. 4-bit pull-up resistors are software assignable to input pins and are automatically disabled for output pins. ports 6 and 7 can be paired to enable 8-bit data transfer. 31-34 (26-29) 35-38 (30-33) ks0-ks3 ks4-ks7 d-4 p8.0-p8.3 p9.0-p9.2 i/o i 4-bit i/o port. 1-bit or 4-bit read/write and test is possible. individual pins are software configurable as input or output. 4-bit pull-up resistors are software assignable to input pins and are automatically disabled for output pins. ports 8 and 9 can be paired to enable 8-bit data transfer. 23-26 (18-21) 40-42 (35-37) ? d-2
product overview k s57c5204/c5208/p5208/c5304/c5308/p5308/c5312/p5312 1- 8 table 1-1. ks57c5204/c5208 pin descriptions (continued) pin name pin type reset value description pin number share pin circu it type dtmf o ? dtmf output. 39 (34) ? g-6 btco i/o i basic timer clock output 16 (10) p4.0 e-2 int0 int1 i i external interrupts. the triggering edge for int0 and int1 is selectable. 1 (39) 2 (40) p1.0 p1.1 a-4 int2 i i quasi-interrupt with detection of rising edges 3 (41) p1.2 a-4 int4 i i external interrupt with detection of rising and falling edges. 4 (42) p1.3 a-4 tclo0 i/o i timer/counter 0 clock output 5 (43) p2.0 d-2 tclo1 i/o i timer/counter 1 clock output 6 (44) p2.1 d-2 clo i/o i clock output 7 (1) p2.2 d-2 buz i/o i 2 khz, 4 khz, 8 khz, or 16 khz frequency output at the watch timer clock frequency of 4.19 mhz for buzzer sound 8 (2) p2.3 d-2 tcl0 i/o i external clock input for timer/counter 0 9 (3) p3.0 d-4 tcl1 i/o i external clock input for timer/counter 1 10 (4) p3.1 d-4 ks0-ks3 ks4-ks7 i/o i quasi-interrupt inputs with falling edge detection 31-34 (26-29) 35-38 (30-33) p6.0-p6.3 p7.0-p7.3 d-4 v dd ? ? power supply 11 (5) ? ? v ss ? ? ground 12 (6) ? ? reset ? ? reset signal 18 (12) ? b x in x out ? ? crystal, or ceramic oscillator signal for main system clock. (for external clock input, use x in and input x in 's reverse phase to x out ) 14 (8) 13 (7) ? ? test ? ? chip test input pin, hold gnd when the device is operating. 15 (9) ? ? nc ? ? no connection (16, 38) ? ? note: parentheses indicate pin number for 44 qfp package.
ks57c5204/c5208/p5208/c5304/c5308/p5308/c5312/p5312 product overview 1- 9 table 1-2. ks57c5304/c5308/c5312 pin descriptions pin name pin type description pin number share pin circuit type p1.0 i 1-bit input port. 1-bit and 4-bit read and test is possible. each bit pull-up resistors are assignable. 23 (25) int0 a-4 p2.0 p2.1 p2.2 p2.3 i/o 4-bit i/o port. 1-bit and 4-bit read/write and test is possible. each individual pin can be assignable as input or output. 4-bit pull-up resisters are software assignable to input pins and are automatically disabled for output pins. 24 (26) 25 (27) 26 (28) 27 (29) tclo0 tclo1 clo buz d-2 p3.0 p3.1 ports 2 and 3 can be paired to enable 8-bit data transfer. 28 (30) 29 (31) tcl0 tcl1 d-4 p4.0 p4.1 p4.2 p4.3 p5.0-p5.3 i/o 4-bit i/o ports. 1-bit and 4-bit read/write and test is possible. each individual pin can be assignable as input or output. 4-bit pull-up resisters are software assignable to input pins and are automatically disabled for output pins. the n-channel open-drain or push-pull output can be selected by software (1-bit unit). ports 4 and 5 can be paired to enable 8-bit data transfer. 5 (5) 6 (6) 8 (8) 9 (10) 10-13 (11-14) btco e-2 p6.0-p6.3 p7.0-p7.3 i/o 4-bit i/o ports. 1-bit and 4-bit read/write and test is possible. each individual pin can be assignable as input or output. 4-bit pull-up resisters are software assignable to input pins and are automatically disabled for output pins. ports 6 and 7 can be paired to enable 8-bit data transfer. 14-17 (15-18) 18-21 (19-22) ks0-ks3 ks4-ks7 d-4
product overview k s57c5204/c5208/p5208/c5304/c5308/p5308/c5312/p5312 1- 10 table 1-2. ks57c5304/c5308/c5312 pin descriptions (continued) pin name i/o type description pin number share pin circuit type dtmf o dtmf output. 22 (23) ? g-6 int0 i external interrupt input. the triggering edge for int0 is selectable. 23 (25) p1.0 a-3 tclo0 i/o timer/counter 0 clock output 24 (26) p2.0 d-2 tclo1 i/o timer/counter 1 clock output 25 (27) p2.1 d-2 clo i/o clock output 26 (28) p2.2 d-2 buz i/o 2 khz, 4 khz, 8 khz, or 16 khz frequency output at the watch timer clock frequency of 4.19 mhz for buzzer sound 27 (29) p2.3 d-2 tcl0 i/o external clock input for timer/counter 0 28 (30) p3.0 d-4 tcl1 i/o external clock input for timer/counter 1 29 (31) p3.1 d-4 btco i/o basic timer clock output 5 (5) p4.0 e-2 v dd ? power supply 30 (32) ? ? v ss ? ground 1 (1) ? ? x in x out ? crystal, or ceramic oscillator signal for main system clock. (for external clock input, use x in and input x in 's reverse phase to x out ) 3 (3) 2 (2) ? ? nc ? no connection (9, 24) ? ? test ? chip test input pin, hold gnd when the device is operating. 4 (4) ? ? reset ? reset signal 7 (7) ? b ks0-ks3 ks4-ks7 i/o quasi-interrupt inputs with falling edge detection 14-17 (15-18) 18-21 (19-22) p6.0-p6.3 p7.0-p7.3 d-4 note: parentheses indicate the pin number for 32-sop package.
ks57c5204/c5208/p5208/c5304/c5308/p5308/c5312/p5312 product overview 1- 11 pin circuit diagrams p-channel n-channel in v dd figure 1-6. pin circuit type a schmitt trigger pull-up resistor v dd resistor enable in p-channel figure 1-7. pin circuit type a-4 schmitt trigger in v dd pull-up resistor figure 1-8. pin circuit type b p-channel n-channel v dd out output disable data figure 1-9. pin circuit type c
product overview k s57c5204/c5208/p5208/c5304/c5308/p5308/c5312/p5312 1- 12 p-channel i/o output disable data circuit type c pull-up enable v dd pull-up resistor figure 1-10. pin circuit type d-2 p-channel i/o output disable data circuit type c pull-up enable v dd schmitt trigger pull-up resistor figure 1-11. pin circuit type d-4 v dd pne output disable data pull-up resistor enable v dd i/o pull-up resistor p-channel n-channel figure 1-12. pin circuit type e-2 dtmf out output disable figure 1-13. pin circuit type g-6
ks57c5204/c5208/p5208/c5304/c5308/p5308/c5312/p5312 electric al data 13- 1 13 electrical data overview in this section, information on ks57c5204/c5208/c5304/c5308/c5312 electrical characteristics is presented as tables and graphics. the information is arranged in the following order: standard electrical characteristics ? absolute maximum ratings ? d.c. electrical characteristics ? system clock oscillator characteristics ? i/o capacitance ? a.c. electrical characteristics ? operating voltage range miscellaneous timing waveforms ? a.c timing measurement point ? clock timing measurement at x in and x out ? tcl timing ? input timing for reset ? input timing for external interrupts stop mode characteristics and timing waveforms ? ram data retention supply voltage in stop mode ? stop mode release timing when ini tiated by reset ? stop mode release timing when initiated by an interrupt request
electrical data ks57c5204 /c5208/p5208/c5304/c5308/p5308/c5312/p5312 13- 2 table 13-1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating units supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v i1 all i/o ports ? 0.3 to v dd + 0.3 v output voltage v o ? ? 0.3 to v dd + 0.3 v output current high i oh one i/o port active ? 15 ma all i/o ports active ? 35 output current low i ol one i/o port active + 30 (peak value) ma + 15 (note) all i/o ports active + 100 (peak value) + 60 (note) operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 c note: the values for output current low ( i ol ) are calculated as peak value duty . table 13-2. d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units input high voltage v ih1 all input pins except those specified below for v ih2 ? v ih3 0.7 v dd ? v dd v v ih2 ports 1, 3, 6, 7, and reset 0.8 v dd v dd v ih3 x in and x out v dd ? 0.1 v dd input low voltage v il1 all input pins except those specified below for v il2 ?v il3 ? ? 0.3 v dd v v il2 ports 1, 3, 6, 7, and reset 0.2 v dd v il3 x in and x out 0.1
ks57c5204/c5208/p5208/c5304/c5308/p5308/c5312/p5312 electric al data 13- 3 table 13-2. d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units output high voltage v oh i oh = ? 1 ma ports except 1 v dd ? 1.0 ? ? v output low voltage v ol1 v dd = 4.5 v to 5.5 v i ol = 15 ma, ports 4 and 5 only ? ? 2 v v dd = 1.8 to 5.5 v, i ol = 1.6ma ? ? 0.4 v ol2 v dd = 4.5 v to 5.5 v i ol = 4 ma, all out ports except 4,5 ? ? 2 v v dd = 1.8 to 5.5 v, i ol = 1.6ma ? ? 0.4 input high leakage current i lih1 v i = v dd all input pins except those specified below ? ? 3 a i lih2 v i = v dd x in and x out 20 input low leakage current i lil1 v i = 0 v all input pins except below and reset ? ? ? 3 a i lil2 v i = 0 v x in and x out only ? 20 output high leakage current i loh v o = v dd all out pins ? ? 3 a output low leakage current i lol v o = 0 v all out pins ? ? ? 3 a pull-up resistor r l1 v dd = 5 v; v i = 0 v except reset 25 47 100 k w v dd = 3 v 50 95 200 r l2 v dd = 5 v; v i = 0 v; reset 100 220 400 v dd = 3 v 200 450 800
electrical data ks57c5204 /c5208/p5208/c5304/c5308/p5308/c5312/p5312 13- 4 table 13-2. d.c. electrical characteristics (concluded) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units supply current (1) i dd1 (dtmf on) run mode; v dd = 5 v 10% (2) 3.58 mhz crystal oscillator, c1 = c2 = 22 pf ? 2.5 5.0 ma v dd = 3 v 10% 1.4 3.0 i dd2 run mode; v dd = 5 v 10% 6.0 mhz ? 2.5 8.0 ma (dtmf off) crystal oscillator, c1 = c2 = 22 pf 3.58 mhz 1.6 4.0 v dd = 3 v 10% 6.0 mhz 1.2 4.0 3.58 mhz 0.7 2.3 i dd3 idle mode; = v dd = 5 v 10% 6.0 mhz ? 0.7 2.5 ma crystal oscillator, c1 = c2 = 22 pf 3.58 mhz 0.6 1.8 v dd = 3 v 10% 6.0 mhz 0.3 1.5 3.58 mhz 0.2 1.0 i dd4 stop mode; v dd = 5 v 10% ? 0.01 3 a stop mode; v dd = 3 v 10% 0.01 2 row tone level v row v dd = 2.0 v to 5.5 v rl = 12 k w , temp = ? 30 c to 60 c ? 16.0 ? 14.0 ? 11.0 dbv ratio of column to row tone db cr v dd = 2.0 v to 5.5 v rl = 12 k w , temp = ? 30 c to 60 c 1 2 3 db distortion (dual tone) thd v dd = 2.0 v to 5.5 v 1mhz band; rl= 12 k w temp = ? 30 c to 60 c ? ? 5 % notes: 1. d.c. electrical values for supply current (i dd1 to i dd3 ) do not include current drawn through internal pull-up registers. 2. for d.c. electrical values , the power control register (pcon) must be set to 0011b.
ks57c5204/c5208/p5208/c5304/c5308/p5308/c5312/p5312 electric al data 13- 5 table 13-3. main system clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5.5 v) oscillator clock configuration parameter test condition min typ max units ceramic oscillator x in c1 c2 x out oscillation frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 1.8 v to 5.5 v 0.4 ? 3 stabilization time (2) v dd = 3 v ? ? 4 ms crystal oscillator x in c1 c2 x out oscillation frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 1.8 v to 5.5 v 0.4 ? 3 stabilization time (2) v dd = 3 v ? ? 10 ms external clock x in x out x in input frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 1.8 v to 5.5 v 0.4 ? 3 x in input high and low level width (t xh , t xl ) ? 83.3 ? 1250 ns notes: 1. oscillation frequency and x in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated.
electrical data ks57c5204 /c5208/p5208/c5304/c5308/p5308/c5312/p5312 13- 6 table 13-4 . recommended oscillator constants (t a = ? 40 c to + 85 c) manufacturer series number (1) frequency range load cap ( pf) oscillator voltage range (v) remarks c1 c2 min max tdk fcr ? e ? m5 3.58 mhz-6.0 mhz 33 33 2.0 5.5 leaded type fcr ? e ? mc5 3.58 mhz-6.0 mhz (2) (2) 2.0 5.5 on-chip c leaded type ccr ? e ? mc3 3.58 mhz-6.0 mhz (3) (3) 2.0 5.5 on-chip c smd type note s: 1. please specify normal oscillator frequency. 2. on-chip c: 30pf built in. 3. on-chip c: 38pf built in. table 13-5. input/output capacitance (t a = 25 c, v dd = 0 v ) parameter symbol condition min typ max units input capacitance c in f = 1 mhz; unmeasured pins are returned to v ss ? ? 15 pf output capacitance c out ? ? 15 pf i/o capacitance c io ? ? 15 pf
ks57c5204/c5208/p5208/c5304/c5308/p5308/c5312/p5312 electric al data 13- 7 table 13-6. a.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units instruction cycle time t cy v dd = 2.7 v to 5.5 v 0.67 ? 64 s v dd = 1.8 v to 5.5 v 1.33 tcl0, tcl1 input frequency f ti0 , f ti1 v dd = 2.7 v to 5.5 v 0 ? 1.5 mhz v dd = 1.8 v to 5.5v 1 mhz tcl0, tcl1 input high, low width t tih0 , t til0 t tih1 , t til1 v dd = 2.7 v to 5.5 v 0.48 ? ? s v dd = 1.8 v to 5.5 v 1.8 interrupt input high, low width t inth , t intl int0, int1, int2, int4, ks0-ks7 10 ? ? s reset input low width t rsl input 10 ? ? s
electrical data ks57c5204 /c5208/p5208/c5304/c5308/p5308/c5312/p5312 13- 8 1.5 mhz cpu clock 0.75 mhz 15.625 khz main oscillator frequency (divided by 4) 3 mhz 6 mhz 1 2 3 4 5 6 7 supply voltage (v) cpu clock = 1/n x oscillator frequency (n = 4, 8 or 64) 2.7 1.8 figure 13-1. standard operating voltage range table 13-7. ram data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr ? 1.8 ? 5.5 v data retention supply current i dddr v dddr = 1.8 v ? 0.1 10 a release signal set time t srel ? 0 ? ? s oscillator stabilization wait t wait released by reset ? 2 17 / fx ? ms time (1) released by interrupt (2) notes: 1. during oscillator stabilization wait time, all cpu operations must be stopped to avoid instability during oscillator start-up. 2. use the basic timer mode register (bmod) interval timer to delay execution of cpu instructions during the wait time.
ks57c5204/c5208/p5208/c5304/c5308/p5308/c5312/p5312 electric al data 13- 9 timing waveforms execution of stop instruction internal reset operation ~ ~ v dddr ~ ~ stop mode idle mode operating mode data retention mode t srel t wait reset v dd figure 13-2. stop mode release timing when initiated by reset execution of stop instruction v dddr ~ ~ data retention v dd normal operating mode ~ ~ stop mode idle mode t srel t wait power-down mode terminating signal (interrupt request) figure 13-3. stop mode release timing when initiated by interrupt request
electrical data ks57c5204 /c5208/p5208/c5304/c5308/p5308/c5312/p5312 13- 10 timing waveforms (continued) 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd measurement points figure 13-4. a.c. timing measurement points (except for x in ) x in t xh t xl 1/fx v dd - 0.1 v 0.1 v figure 13-5. clock timing measurement at x in tcl t tih t til 1/f ti 0.8 v dd 0.2 v dd figure 13-6. tcl timing
ks57c5204/c5208/p5208/c5304/c5308/p5308/c5312/p5312 electric al data 13- 11 reset t rsl 0.2 v dd figure 13-7. input timing for reset signal int0, 1, 2, 4, ks0 to ks7 t inth t intl 0.8 v dd 0.2 v dd figure 13-8. input timing for external interrupts and quasi-interrupts
electrical data ks57c5204 /c5208/p5208/c5304/c5308/p5308/c5312/p5312 13- 12 notes
ks57c5204/c5208/p5208/c5304/c5308/p5308/c5312/p5312 mechanical data 14- 1 14 mechanical data overview the ks57c5204/c5208 microcontroller are available in a 42-pin sdip package (42-sdip-600), and a 44-pin qfp package (44-qfp-1010b). the ks57c5304/c5308/c5312 microcontrollers are available in a 30-pin sdip package (30-sdip-400) and a 32-pin sop package (32-sop-450a). note : dimensions are in millimeters. 39.50 max 39.10 0 .2 0.50 0.1 1.778 (1.77) 0.51 min 3.30 0.3 3.50 0.2 5.08 max 42-sdip-600 0-15 1.00 0.1 0.25 + 0.1 - 0.05 15.24 14.00 0 .2 #42 #22 #21 #1 figure 14-1. 42 - sdip - 600 package dimensions
mechanical data ks57c5204/c5208/p52 08/c5304/c5308/p5308/c5312/p5312 14- 2 44-qfp-1010b #44 note : dimensions are in millimeters. 10.00 0.2 13.20 0.3 10.00 0.2 13.20 0.3 #1 0.35 + 0.10 - 0.05 0.80 (1.00) 0.10 max 0.80 0.20 0.05 min 2.05 0.10 2.30 max 0.15 + 0.10 - 0.05 0-8 figure 14-2. 44-qfp-1010b package dimensions
ks57c5204/c5208/p5208/c5304/c5308/p5308/c5312/p5312 mechanical data 14- 3 note : dimensions are in millimeters. 27.88 max 27.48 0 .2 0.56 0.1 1.778 (1.77) 0.51 min 3.30 0.3 3.81 0.2 5.08 max 30-sdip-400 0-15 1.12 0.1 0.25 + 0.1 - 0.05 10.16 8.94 0 .2 #30 #16 #15 #1 figure 14-3. 30 - sdip - 400 package dimensions
mechanical data ks57c5204/c5208/p52 08/c5304/c5308/p5308/c5312/p5312 14- 4 32-sop-450a #1 #16 #17 #32 2.40 max (0.43) 0.05 min 1.27 note: dimensions are in millimeters 19.90 0 .2 0.40 0 .1 12.00 0 .3 2.00 0 .2 11.43 0-8 8.34 0 .2 0.78 0 .2 0.20 + 0.1 - 0.05 figure 14-4. 32-sop-450a package dimensions
ks57c5204/c5208/p5208/c5304/c5308/p5308/c5312/p5312 ks57p520 8/p5308/p5312 otp 15- 1 1 5 ks57p5208/p5308/p5312 otp overview the ks57p5208/p5308/p5312 single-chip cmos microcontroller is the otp (one time programmable) version of the ks57c5204/c5208/c5304/c5308/c5312 microcontroller. it has an on-chip eprom instead of masked rom. the eprom is accessed by a serial data format. the ks57p5208/p5308/p5312 is fully compatible with the ks57c5208/c5308/c5312, both in function and in pin configuration. because of its simple programming requirements, the ks57p5208/p5308/p5312 is ideal for use as an evaluation chip for the ks57c5208/c5308/c5312. p1.0/int0 p1.1/int1 p1.2/int2 p1.3/int4 p2.0/tclo0 p2.1/tclo1 p2.2/clo p2.3/buz sdat /p3.0/tcl0 sclk /p3.1/tcl1 v dd /v dd v ss /v ss x out x in v pp /test p4.0/btco p4.1 reset / reset p3.2 p3.3 p4.2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 p9.2 p9.1 p9.0 dtmf p7.3/ks7 p7.2/ks6 p7.1/ks5 p7.0/ks4 p6.3/ks3 p6.2/ks2 p6.1/ks1 p6.0/ks0 p5.3 p5.2 p5.1 p5.0 p8.3 p8.2 p8.1 p8.0 p4.3 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 ks57p5208 (42-sdip-600) figure 15-1. ks57p5208 pin assignment diagram (42-sdip)
ks57p5208/p5308/p5312 otp ks57c5204/c5208/p5208/c5304/c5308/p5308/c5312/p5312 15- 2 dtmf p9.0 p9.1 p9.2 nc p1.0/int0 p1.1/int1 p1.2/int2 p1.3/int4 p2.0/tclo0 p2.1/tclo1 ks57p5208 (44-qfp-1010b) 1 2 3 4 5 6 7 8 9 10 11 p7.3/ks7 p7.2/ks6 p7.1/ks5 p7.0/ks4 p6.3/ks3 p6.2/ks2 p6.1/ks1 p6.0/ks0 p5.3 p5.2 p5.1 p5.0 p8.3 p8.2 p8.1 p8.0 p4.3 nc p4.2 p3.3 p3.2 reset/ reset 34 35 36 37 38 39 40 41 42 43 44 p2.2/clo p2.3/buz sdat /p3.0/tcl0 sclk /p3.1/tcl1 v dd /v dd v ss /v ss x out x in v pp /test p4.0/btco p4.1 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 figure 15-2. ks57p5208 pin assignment diagram (44-qfp)
ks57c5204/c5208/p5208/c5304/c5308/p5308/c5312/p5312 ks57p520 8/p5308/p5312 otp 15- 3 v ss /v ss x out x in v pp /test p4.0/btco p4.1 reset /reset p4.2 p4.3 p5.0 p5.1 p5.2 p5.3 p6.0/ks0 p6.1/ks1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 v dd / v dd p3.1/tcl1/ sclk p3.0/tcl0/ sdat p2.3/buz p2.2/clo p2.1/tclo1 p2.0/tclo0 p1.0/int0 dtmf p7.3/ks7 p7.2/ks6 p7.1/ks5 p7.0/ks4 p6.3/ks3 p6.2/ks2 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ks57p5308/p5312 (30-sdip-400) figure 15-3. ks57p5308/p5312 pin assignment diagram (30-sdip) v ss /v ss x out x in v pp /test p4.0/btco p4.1 reset /reset p4.2 nc p4.3 p5.0 p5.1 p5.2 p5.3 p6.0/ks0 p6.1/ks1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v dd / v dd p3.1/tcl1/ sclk p3.0/tcl0/ sdat p2.3/buz p2.2/clo p2.1/tclo1 p2.0/tclo0 p1.0/int0 nc dtmf p7.3/ks7 p7.2/ks6 p7.1/ks5 p7.0/ks4 p6.3/ks3 p6.2/ks2 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 ks57p5308/p5312 (32-sop-450a) figure 15-4. ks57p5308/p5312 pin assignment diagram (32-sop)
ks57p5208/p5308/p5312 otp ks57c5204/c5208/p5208/c5304/c5308/p5308/c5312/p5312 15- 4 table 15-1. ks57p5208 pin descriptions used to read/write the eprom main chip during programming pin name pin name pin no. i/o function p3.0 sdat 9 (3) i/o serial data pin. output port when reading and input port when writing. can be assigned as a input / push-pull output port. p3.1 sclk 10 (4) i/o serial clock pin. input only pin. test v pp (test) 15 (9) i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. (option) hold gnd when opt is operating. reset reset 18 (12) i chip initialization v dd / v ss v dd / v ss 11/12 (5/6) i logic power supply pin. v dd should be tied to +5 v during programming. note: parentheses indicate pin numbers of 44 qfp package. table 15-2. ks57p5308/p5312 pin descriptions used to read/write the eprom main chip during programming pin name pin name pin no. i/o function p3.0 sdat 28 (30) i/o serial data pin. output port when reading and input port when writing. can be assigned as a input / push-pull output port. p3.1 sclk 29 (31) i/o serial clock pin. input only pin. test v pp (test) 4 (4) i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. (option) hold gnd when opt is operating. reset reset 7 (7) i chip initialization v dd / v ss v dd / v ss 30/1 (32/1) i logic power supply pin. v dd should be tied to +5 v during programming. note: parentheses indicate pin numbers of 32 sdip package.
ks57c5204/c5208/p5208/c5304/c5308/p5308/c5312/p5312 ks57p520 8/p5308/p5312 otp 15- 5 table 15-3. comparison of ks57p5208 and ks57c5208 features characteristic ks57p5208 ks57c5208 program memory 8 k byte eprom 8 k byte mask rom operating voltage (v dd ) 1.8 v (3 mhz) to 5.5 v 1.8 v (3 mhz) to 5.5 v otp programming mode v dd = 5 v, v pp (test) = 12.5 v ? pin configuration 42 sdip / 44 qfp 42 sdip / 44 qfp eprom programmability user program 1 time programmed at the factory table 15-4. comparison of ks57p5308/p5312 and ks57c5308/c5312 features characteristic ks57p5308/p5312 ks57c5308/c5312 program memory 8 k byte eprom / 12 k (p5312) 8 k byte mask rom / 12 k (c5312) operating voltage (v dd ) 1.8 v (3 mhz) to 5.5 v 1.8 v (3 mhz) to 5.5 v otp programming mode v dd = 5 v, v pp (test) = 12.5 v ? pin configuration 30 sop / 32 sop 30 sop / 32 sop eprom programmability user program 1 time programmed at the factory operating mode characteristics when 12.5 v is supplied to the vpp(test) pin of the ks57p5208/p5308/p5312, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 15-3 below. table 15-5. operating mode selection criteria v dd vpp (test) reg/ mem address (a15-a0) r/ w mode 5 v 5 v 0 0000h 1 eprom read 12.5v 0 0000h 0 eprom program 12.5v 0 0000h 1 eprom verify 12.5v 1 0e3fh 0 eprom read protection note: "0" means low level; "1" means high level.
ks57p5208/p5308/p5312 otp ks57c5204/c5208/p5208/c5304/c5308/p5308/c5312/p5312 15- 6 otp electrical data table 15-6. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating units supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v i1 all i/o ports ? 0.3 to v dd + 0.3 v output voltage v o ? ? 0.3 to v dd + 0.3 v output current high i oh one i/o port active ? 15 ma all i/o ports active ? 35 output current low i ol one i/o port active + 30 (peak value) ma + 15 (note) all i/o ports active + 100 (peak value) + 60 (note) operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 c note: the values for output current low ( i ol ) are calculated as peak value duty . table 15-7. d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units input high voltage v ih1 all input pins except those specified below for v ih2 ? v ih3 0.7 v dd ? v dd v v ih2 ports 1, 3, 6, 7, and reset 0.8 v dd v dd v ih3 x in and x out v dd ? 0.1 v dd input low voltage v il1 all input pins except those specified below for v il2 ?v il3 ? ? 0.3 v dd v v il2 ports 1, 3, 6, 7, and reset 0.2 v dd v il3 x in and x out 0.1
ks57c5204/c5208/p5208/c5304/c5308/p5308/c5312/p5312 ks57p520 8/p5308/p5312 otp 15- 7 table 15-7. d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units output high voltage v oh i oh = ? 1 ma ports except 1 v dd ? 1.0 ? ? v output low voltage v ol1 v dd = 4.5 v to 5.5 v i ol = 15 ma, ports 4 and 5 only ? ? 2 v v dd = 1.8 to 5.5 v, i ol = 1.6ma ? ? 0.4 v ol2 v dd = 4.5 v to 5.5 v i ol = 4 ma, all out ports except 4,5 ? ? 2 v v dd = 1.8 to 5.5 v, i ol = 1.6ma ? ? 0.4 input high leakage current i lih1 v i = v dd all input pins except those specified below ? ? 3 a i lih2 v i = v dd x in and x out 20 input low leakage current i lil1 v i = 0 v all input pins except below and reset ? ? ? 3 a i lil2 v i = 0 v x in and x out only ? 20 output high leakage current i loh v o = v dd all out pins ? ? 3 a output low leakage current i lol v o = 0 v all out pins ? ? ? 3 a pull-up resistor r l1 v dd = 5 v; v i = 0 v except reset 25 47 100 k w v dd = 3 v 50 95 200 r l2 v dd = 5 v; v i = 0 v; reset 100 220 400 v dd = 3 v 200 450 800
ks57p5208/p5308/p5312 otp ks57c5204/c5208/p5208/c5304/c5308/p5308/c5312/p5312 15- 8 table 15-7. d.c. electrical characteristics (concluded) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units supply current (1) i dd1 (dtmf on) run mode; v dd = 5 v 10% (2) 3.58 mhz crystal oscillator, c1 = c2 = 22 pf ? 2.5 5.0 ma v dd = 3 v 10% 1.4 3.0 i dd2 run mode; v dd = 5 v 10% 6.0 mhz ? 2.5 8.0 ma (dtmf off) crystal oscillator, c1 = c2 = 22 pf 3.58 mhz 1.6 4.0 v dd = 3 v 10% 6.0 mhz 1.2 4.0 3.58 mhz 0.7 2.3 i dd3 idle mode; = v dd = 5 v 10% 6.0 mhz ? 0.7 2.5 ma crystal oscillator, c1 = c2 = 22 pf 3.58 mhz 0.6 1.8 v dd = 3 v 10% 6.0 mhz 0.3 1.5 3.58 mhz 0.2 1.0 i dd4 stop mode; v dd = 5 v 10% ? 0.01 3 a stop mode; v dd = 3 v 10% 0.01 2 row tone level v row v dd = 2.0 v to 5.5 v rl = 12 k w , temp = ? 30 c to 60 c ? 16.0 ? 14.0 ? 11.0 dbv ratio of column to row tone db cr v dd = 2.0 v to 5.5 v rl = 12 k w , temp = ? 30 c to 60 c 1 2 3 db distortion (dual tone) thd v dd = 2.0 v to 5.5 v 1mhz band; rl= 12 k w temp = ? 30 c to 60 c ? ? 5 % notes: 1. d.c. electrical values for supply current (i dd1 to i dd3 ) do not include current drawn through internal pull-up registers. 2. for d.c. electrical values , the power control register (pcon) must be set to 0011b.
ks57c5204/c5208/p5208/c5304/c5308/p5308/c5312/p5312 ks57p520 8/p5308/p5312 otp 15- 9 table 15-8. main system clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5.5 v) oscillator clock configuration parameter test condition min typ max units ceramic oscillator x in c1 c2 x out oscillation frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 1.8 v to 5.5 v 0.4 ? 3 stabilization time (2) v dd = 3 v ? ? 4 ms crystal oscillator x in c1 c2 x out oscillation frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 1.8 v to 5.5 v 0.4 ? 3 stabilization time (2) v dd = 3 v ? ? 10 ms external clock x in x out x in input frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 1.8 v to 5.5 v 0.4 ? 3 x in input high and low level width (t xh , t xl ) ? 83.3 ? 1250 ns notes: 1. oscillation frequency and x in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated.
ks57p5208/p5308/p5312 otp ks57c5204/c5208/p5208/c5304/c5308/p5308/c5312/p5312 15- 10 table 15-9. input/output capacitance (t a = 25 c, v dd = 0 v ) parameter symbol condition min typ max units input capacitance c in f = 1 mhz; unmeasured pins are returned to v ss ? ? 15 pf output capacitance c out ? ? 15 pf i/o capacitance c io ? ? 15 pf table 15-10. a.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units instruction cycle time t cy v dd = 2.7 v to 5.5 v 0.67 ? 64 s v dd = 1.8 v to 5.5 v 1.33 tcl0, tcl1 input frequency f ti0 , f ti1 v dd = 2.7 v to 5.5 v 0 ? 1.5 mhz v dd = 1.8 v to 5.5v 1 mhz tcl0, tcl1 input high, low width t tih0 , t til0 t tih1 , t til1 v dd = 2.7 v to 5.5 v 0.48 ? ? s v dd = 1.8 v to 5.5 v 1.8 interrupt input high, low width t inth , t intl int0, int1, int2, int4, ks0-ks7 10 ? ? s reset input low width t rsl input 10 ? ? s
ks57c5204/c5208/p5208/c5304/c5308/p5308/c5312/p5312 ks57p520 8/p5308/p5312 otp 15- 11 1.5 mhz cpu clock 0.75 mhz 15.625 khz main oscillator frequency (divided by 4) 3 mhz 6 mhz 1 2 3 4 5 6 7 supply voltage (v) cpu clock = 1/n x oscillator frequency (n = 4, 8 or 64) 2.7 1.8 figure 15-5. standard operating voltage range table 15-11. ram data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr ? 1.8 ? 5.5 v data retention supply current i dddr v dddr = 1.8 v ? 0.1 10 a release signal set time t srel ? 0 ? ? s oscillator stabilization wait t wait released by reset ? 2 17 / fx ? ms time (1) released by interrupt (2) notes: 1. during oscillator stabilization wait time, all cpu operations must be stopped to avoid instability during oscillator start-up. 2. use the basic timer mod e register (bmod) interval timer to delay execution of cpu instructions during the wait time.
ks57p5208/p5308/p5312 otp ks57c5204/c5208/p5208/c5304/c5308/p5308/c5312/p5312 15- 12 notes

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